ics512 loco? pll clock multiplier mds 512 c 1 revision 061900 printed 11/13/00 inte g rated circuit systems, inc. ? 525 race street ? san jose ?ca?95126?(408) 295-9800tel ? www.icst.com ? packaged as 8 pin soic or die ? upgrade of popular ics502 with: - changed multiplier table - higher operating frequencies ? zero ppm multiplication error ? easy to cascade with other 5xx series ? input crystal frequency of 5 - 27 mhz ? input clock frequency of 2 - 50 mhz ? output clock frequencies up to 200 mhz ? compatible with all popular cpus ? duty cycle of 45/55 up to 200 mhz ? mask option for 9 selectable frequencies ? operating voltages of 3.0 to 5.5v ? industrial temperature version available ? advanced, low power cmos process the ics512 loco? is the most cost effective way to generate a high quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. the name loco stands for low cost oscillator, as it is designed to replace crystal oscillators in most electronic systems. using phase-locked-loop (pll) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 mhz. with a reference output, this chip plus an inexpensive crystal can replace two oscillators. stored in the chips rom is the ability to generate nine different popular multiplication factors, allowing one chip to output many common frequencies (see page 2). block diagram description features crystal or clock in p ut x1/iclk x2 o p tional crystal ca p acitors clk crystal oscillator vdd gnd pll clock synthesis and control circuitry output buffer ref output buffer s1, s0 2
ics512 loco? pll clock multiplier mds 512 c 2 revision 061900 printed 11/13/00 inte g rated circuit systems, inc. ? 525 race street ? san jose ?ca?95126?(408) 295-9800tel ? www.icst.com pin assignment 18 2 3 4 7 6 5 x1/iclk vdd gnd ref x2 s1 s0 clk number name type description 1 x1/iclk xi crystal connection or clock input. 2 vdd p connect to +3.3v or +5v. 3 gnd p connect to ground. 4 ref o buffered crystal oscillator output clock. 5 clk o clock output per table above. 6 s0 t i multiplier select pin 0. connect to gnd or vdd or float (no connection). 7 s1 t i multiplier select pin 1. connect to gnd or vdd or float (no connection). 8 x2 xo crystal connection. leave unconnected for clock input. pin descriptions key: xi/xo = crystal connections, ti = tri-level in p ut, o = out p ut, p = p ower su pp ly connection s1 s0 clk 0 0 4x input 0 m 5.333x input 0 1 5x input m 0 2.5x input m m 2x input m 1 3.333x input 1 0 6x input 1 m 3x input 1 1 8x input clock output table 0 = connect directly to ground. 1 = connect directly to vdd. m = leave unconnected (floatin g ). output 20 24 30 32 33.33 37.5 40 48 50 60 64 input 10 12 10 16 16.66 15 10 12 20 10 16 selection (s1, s0) m, m m, m 1, m m, m m, m m, 0 0, 0 0, 0 m, 0 1, 0 0, 0 output 66.66 72 75 80 83.33 90 100 120 125 133.33 150 input 20 12 25 10 25 15 20 15 25 25 25 selection (s1, s0) m, 1 1, 0 1, m 1, 1 m, 1 1, 0 0, 1 1, 1 0, 1 0, m 1, 0 common output frequencies examples (mhz) note that all of the above outputs are achieved by using a common, inexpensive 10mhz to 25mhz crystal. consult ics on how to achieve other out p ut fre q uencies.
ics512 loco? pll clock multiplier mds 512 c 3 revision 061900 printed 11/13/00 inte g rated circuit systems, inc. ? 525 race street ? san jose ?ca?95126?(408) 295-9800tel ? www.icst.com electrical specifications parameter conditions minimum typical maximum units absolute maximum ratings (stresses b e e ond these can p erman e e ntl dama g e t t he device) supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+0.5 v clock output referenced to gnd -0.5 vdd+0.5 v ambient operating temperature 0 70 c ICS512MI only -40 85 c soldering temperature max of 10 seconds 260 c storage temperature -65 150 c dc characteristics (vdd = 3.3v unless o o therwise noted) operating voltage, vdd 3 5.5 v input high voltage, vih, iclk only iclk (pin 1) (vdd/2)+1 vdd/2 v input low voltage, vil, iclk only iclk (pin 1) vdd/2 (vdd/2)-1 v input high voltage, vih s0, s1 vdd-0.5 v input low voltage, vil s0, s1 0.5 v output high voltage, voh, cmos high ioh=-8ma vdd-0.4 v output high voltage, voh ioh=-12ma 2.4 v output low voltage, vol iol=12ma 0.4 v idd operating supply current, 20 mhz crystal no load, 100mhz 9 ma short circuit current clk output 70 ma input capacitance, s1, s0 pins 6, 7 4 pf ac characteristics (vdd = 3.3v unless o o therwise noted) input frequency, crystal input 5 27 mhz input frequency, clock input 2 50 mhz output frequency, vdd = 4.5 to 5.5v 0 to +70 c 14 200 mhz note 1 -40 to +85 c 14 160 mhz output frequency, vdd = 3.0 to 3.6v 0 to +70 c 14 160 mhz note 1 -40 to +85 c 14 145 mhz output clock rise time 0.8 to 2.0v 1 ns output clock fall time 2.0 to 0.8v 1 ns output clock duty cycle at vdd/2 45 49 to 51 55 % absolute clock period jitter deviation from mean 200 ps one si g ma clock period jitter 80 p s note 1: the phase relationship between input and output clocks can change at power up. for a fixed phase relationship, see the ics570 or the ics527.
ics512 loco? pll clock multiplier mds 512 c 4 revision 061900 printed 11/13/00 inte g rated circuit systems, inc. ? 525 race street ? san jose ?ca?95126?(408) 295-9800tel ? www.icst.com while the information presented herein has been checked for both accuracy and reliability, ics assumes no responsibility for ei ther its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this pro duct is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environment al requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not au thorize or warrant any ics product for use in life support devices or critical medical instruments. ordering information part/order number marking package temperature ics512m ics512m 8 pin soic 0 to 70 c ics512mt ics512m 8 pin soic on tape and reel 0 to 70 c ICS512MI ics512i 8 pin soic -40 to +85 c ICS512MIt ics512i 8 p in soic on ta p e and reel -40 to +85 c external components / crystal selection the ics512 requires a 0.01f decoupling capacitor to be connected between vdd and gnd. it must be connected close to the ics512 to minimize lead inductance. no external power supply filtering is required for this device. a 33 w terminating resistor can be used next to the clk and ref pins. the total on-chip capacitance is approximately 15 pf, so a parallel resonant, fundamental mode crystal should be used. for crystals with a specified load capacitance greater than 15 pf, crystal capacitors should be connected from each of the pins x1 and x2 to ground as shown in the block diagram on page 1. the value (in pf) of these crystal caps should be = (c l -15)*2, where c l is the crystal load capacitance in pf. these external capacitors are only required for applications where the exact frequency is critical. for a clock input, connect to x1 and leave x2 unconnected (no ca p acitors on either). loco is a trademark of ics package outline and package dimensions (for current dimensional specifications, see jedec 95.) b d eh e a1 c a h x 45 l index area 12 8 p in soic inc h h es milli m m eters symbol min max min max a 0.0532 0.0688 1.35 1.75 a1 0.0040 0.0098 0.10 0.24 b 0.0130 0.0200 0.33 0.51 c 0.0075 0.0098 0.19 0.24 d 0.1890 0.1968 4.80 5.00 e 0.1497 0.1574 3.80 4.00 e .050 b s s c 1.27 b s s c h 0.2284 0.2440 5.80 6.20 h 0.0099 0.0195 0.25 0.50 l 0.0160 0.0500 0.41 1.27
|
